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An Ultra High-Frequency 8-Channel Neurostimulator Circuit with 68% Peak Power Efficiency
Alessandro Urso, Marijn Van Dongen, Wouter Serdijn
Session: Poster session II
Session starts: Thursday 24 January, 16:00
Alessandro Urso (Delft University of Technology)
Marijn Van Dongen ()
Wouter Serdijn (Delft University of Technology)
Abstract:
In order to recruit neurons in the targeted tissue, constant-current neural stimulators are
usually used. Recently, Ultra High-Frequency (UHF) stimulation has been proposed and
proved to have the same efficacy of constant current stimulation [1]. The total number of
external components is reduced, while the power efficiency is increased. This leads to a
smaller stimulator device with an increased battery life.
The core circuit of the UHF neurostimulator is a DC-DC converter, which generates current
pulses. Each stimulation phase is made of a burst of current pulses injected into the tissue at a
determined frequency. The amplitude of the pulses is controlled by means of a duty cycle
signal.
Here, we present the design guidelines and the IC measurement results of a power-efficient
UHF neural stimulator. An overall peak power efficiency of 68% is achieved when 8
independent channels with 16 fully configurable electrodes are used. The only external
component is an inductor. It is operated in a time-interleaved fashion across all the activated
channels. A novel zero-current detection scheme is proposed. It does not require the freewheel
diode usually used in DC-DC converters to prevent current flow from the load back to the
inductor. A gate-driver circuit is implemented. It allows to use thin gate oxide transistors as
high voltage switches. By doing so, the external high voltage supply, usually used in neural
stimulators, is avoided and the neurostimulator is powered from a 3.5 V input voltage. Both
the current-detection technique and the gate-driving circuit allow to boost the power
efficiency by 200% when compared to previous implementations of high-frequency neural
stimulators [1], [2]. The circuit is implemented in a 0.18 μm HV CMOS process, and the total
chip area is 3.65 mm 2 .